Error modeling in semiconductor memory of computers

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DC Field	Value	Language
dc.contributor.author	Urbanovich, P.	en
dc.date.accessioned	2019-11-16T11:01:36Z	-
dc.date.available	2019-11-16T11:01:36Z	-
dc.date.issued	2019	-
dc.identifier.citation	Urbanovich, P. Error modeling in semiconductor memory of computers / P. Urbanovich // Proc. of 11th Intern. Conf. NEET’2019, Zakopane, Poland, June 25 - 28, 2019. – Lublin University of Techn., 2019. – P. 30.	en
dc.identifier.uri	https://elib.belstu.by/handle/123456789/31445	-
dc.description	Defects in semiconductor memory chips and errors of their functioning are of interest to both manufacturers of memory and their consumers. Memory errors can be classified into soft errors, which randomly corrupt bits but do not leave physical damage; and hard errors, which corrupt bits in a repeatable manner because of a physical defect. Some time ago numerous studies concerning the distribution of failures and bit errors in chips and semiconductor memory systems were conducted.	en
dc.subject	Error modeling	en
dc.subject	semiconductor memory of computers	en
dc.title	Error modeling in semiconductor memory of computers	en
dc.type	Article	en
Appears in Collections:	Статьи в зарубежных изданиях

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