Please use this identifier to cite or link to this item:
https://elib.belstu.by/handle/123456789/31445| Title: | Error modeling in semiconductor memory of computers |
| Authors: | Urbanovich, P. |
| Keywords: | Error modeling semiconductor memory of computers |
| Issue Date: | 2019 |
| Citation: | Urbanovich, P. Error modeling in semiconductor memory of computers / P. Urbanovich // Proc. of 11th Intern. Conf. NEET’2019, Zakopane, Poland, June 25 - 28, 2019. – Lublin University of Techn., 2019. – P. 30. |
| Description: | Defects in semiconductor memory chips and errors of their functioning are of interest to both manufacturers of memory and their consumers. Memory errors can be classified into soft errors, which randomly corrupt bits but do not leave physical damage; and hard errors, which corrupt bits in a repeatable manner because of a physical defect. Some time ago numerous studies concerning the distribution of failures and bit errors in chips and semiconductor memory systems were conducted. |
| URI: | https://elib.belstu.by/handle/123456789/31445 |
| Appears in Collections: | Публикации в зарубежных изданиях |
Files in This Item:
| File | Description | Size | Format | |
|---|---|---|---|---|
| NEET'2019-1.pdf | 106.55 kB | Adobe PDF | View/Open |
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